SCHCR0 (DDR_PHY) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SCHCR0 (DDR_PHY) Register Description

Register NameSCHCR0
Offset Address0x0000000168
Absolute Address 0x00FD080168 (DDR_PHY)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionScheduler Command Register 0

SCHCR0 (DDR_PHY) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0Return zeroes on reads.
SCHDQV24:16rwNormal read/write0x0Scheduler Command DQ Value. Specifies the value to be driven on the
DQ bus during a mode register set command in per-DRAM
addressability mode (DDR4 only). Each bit specifies a value to be
driven on all DQ bits for a lane. Bit [0] is for the DQ bits on lane 0, bit [1]
is for the DQ bits on lane 1, etc.
Reserved15:12roRead-only0x0Return zeroes on reads.
SP_CMD11:8rwNormal read/write0x0Special Command codes: Only applicable when CMD field is set to
SPECIAL_COMMAND(4'b0111)
Valid values are:
4'b0000 = RESET_LO
4'b0001 = RESET_HI
4'b0010 = CKE_LO
4'b0011 = CKE_HI
4'b0100 = CK_STOP
4'b0101 = CK_START
4'b0110 = ODT_ON
4'b0111 = ODT_OFF
4'b1000 - 4'b1101 = RESERVED
4'b1110 = RDIMMCRW
4'b1111 = MODE_EXIT
CMD 7:4rwNormal read/write0x0Specifies the Command to be issued.
Valid values are:
4'b0000 = NOP
4'b0001 = LOAD_MODE
4'b0010 = SELF_REFRESH
4'b0011 = REFRESH
4'b0100 = PRECHARGE
4'b0101 = PRECHAREGE_ALL
4'b0110 = ACTIVATE
4'b0111 = SPECIAL_COMMAND
4'b1000 = WRITE
4'b1001 = WRITE_PRECHG
4'b1010 = READ
4'b1011 = READ_PRECHG
4'b1100 = ZQCAL_SHORT
4'b1101 = ZQCAL_LONG
4'b1110 = POWER_DOWN
4'b1111 = SDRAM_NOP
SCHTRIG 3:0wtcReadable, write a 1 to clear0x0Mode Register Command Trigger: Initialization Trigger: A write of '1' to
this bit triggers the mode register command FSM to issue commands
specified in bits [11:2] of this register. A bit setting of 1 means the step
will be executed as part of the sequence, while a setting of '0' means the
step will be bypassed. The Mod Register Set trigger bit is self-clearing.