SCHCR1 (DDR_PHY) Register Description
| Register Name | SCHCR1 |
|---|---|
| Offset Address | 0x000000016C |
| Absolute Address | 0x00FD08016C (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Scheduler Command Register 1 |
SCHCR1 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SCRNK | 31:28 | rwNormal read/write | 0x0 | Scheduler Rank Address: When set a the corresponding mode register is accessed. Only valid when the ALLRANK value is b0 |
| SCADDR | 27:8 | rwNormal read/write | 0x0 | Scheduler Command Address Specifies the value to be driven on the address bus. |
| SCBG | 7:6 | rwNormal read/write | 0x0 | Scheduler Command Bank Group: Specifies the value to be driven on BG[1:0]. |
| SCBK | 5:4 | rwNormal read/write | 0x0 | Scheduler Command Bank Address: Specifies the value to be driven on BA[1:0]. |
| Reserved | 3 | roRead-only | 0x0 | Return zeroes on reads. |
| ALLRANK | 2 | rwNormal read/write | 0x0 | All Ranks enabled: When set the commands issued by the mode register command FSM are set to all ranks. |
| Reserved | 1:0 | roRead-only | 0x0 | Return zeroes on reads. |