SCR (R5_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SCR (R5_ETM_0) Register Description

Register NameSCR
Offset Address0x0000000014
Absolute Address 0x00FEBFC014 (CORESIGHT_R5_ETM_0)
Width32
TyperoRead-only
Reset Value0x0002000C
DescriptionSystem Configruation Register

SCR (R5_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
No_fetch_cmp17roRead-only0x1No Fetch comparisons. Address comparators are not capable of performing fetch-stage comparisons. Setting bits [2:0] of an Address Access Type Register to b000 (instruction fetch) causes the comparator to have UNPREDICTABLE behavior.
No_of_sup_cores14:12roRead-only0x0Number of supported cores minus 1. The value given here is the maximum value that can be written to bits [27:25] of the Control Register.
Port_mode11roRead-only0x0Port mode supported.
Port_size10roRead-only0x0Port size supported.
Max_port_size_3 9roRead-only0x0Maximum port size[3]. This bit is used in conjunction with bits [2:0].
Fifofull_support 8roRead-only0x0If set to 1, FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETM Configuration Register.
Full_rate 4roRead-only0x0Full-rate clocking is no longer supported.
Half_rate 3roRead-only0x1All modes use half-rate clocking.
Max_port_size_2_0 2:0roRead-only0x4Maximum port size[2:0]. This bit is used in conjunction with bit [9].