SEQ_AVERAGE0 (PLSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SEQ_AVERAGE0 (PLSYSMON) Register Description

Register NameSEQ_AVERAGE0
Offset Address0x0000000128
Absolute Address 0x00FFA50D28 (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionSequencer Channel Averaging, Group 0.

Enable averaging over multiple readings on a per channel basis for group 0 channels. 0: disabled. 1: enabled. The enable and averaging size are selected by Config_Reg0[13:12].

SEQ_AVERAGE0 (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
average015:0rwNormal read/write0x0Bits[4:0] are reserved.
Bit[5] is for VCC_PSINTLP.
Bit[6] is for VCC_PSINTFP.
Bit[7]
is for VCC_PSAux.
Bit[8] is for Temp_PL.
Bit[9] is for PL VCCINT.
Bit[10] is for PL VCCAUX.
Bit[11] is reserved.
Bit[12] is reserved.
Bit[13] is reserved.
Bit[14] is for PL VCCBRAM.
Bit[15] is reserved.