SEQ_CHANNEL0 (PSSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SEQ_CHANNEL0 (PSSYSMON) Register Description

Register NameSEQ_CHANNEL0
Offset Address0x0000000120
Absolute Address 0x00FFA50920 (AMS_PS_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionSequencer Channel Inclusion, Group 0.

Include these channels in the auto-sequencing measurement mechanism performed by the PS SysMon unit. 0: exclude channel. 1: include channel. Note: the channel ordering for this register is irregular; the upper 8 bits are swapped with the lower 8 bits.

SEQ_CHANNEL0 (PSSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
supply314rwNormal read/write0x0VCC_PSAUX
supply210rwNormal read/write0x0VCC_PSINTFP
supply1 9rwNormal read/write0x0VCC_PSINTLP
temperature 8rwNormal read/write0x0Temp_LPD, temperature diode is located in the PS SysMon which is near RPU in LPD domain.
supply6 7rwNormal read/write0x0VCCO_PSIO0
supply5 6rwNormal read/write0x0VCCO_PSIO3
supply4 5rwNormal read/write0x0VCCO_PSDDR
calibration 0rwNormal read/write0x0Calibration.