SEQ_CHANNEL1 (PLSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SEQ_CHANNEL1 (PLSYSMON) Register Description

Register NameSEQ_CHANNEL1
Offset Address0x0000000124
Absolute Address 0x00FFA50D24 (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionSequencer Channel Inclusion, Group 1.

Include or exclude channels in the auto-sequencing routine. 0: exclude channel. 1: include channel. Each of the 16 VAUX channels consist of two analog signals that are routed by the user. Note: UG580 refers to this register as SEQCHSEL2.

SEQ_CHANNEL1 (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Vaux0F15rwNormal read/write0x0VAux15 channel.
Vaux0E14rwNormal read/write0x0VAux14 channel.
Vaux0D13rwNormal read/write0x0VAux13 channel.
Vaux0C12rwNormal read/write0x0VAux12 channel.
Vaux0B11rwNormal read/write0x0VAux11 channel.
Vaux0A10rwNormal read/write0x0VAux10 channel.
Vaux09 9rwNormal read/write0x0VAux9 channel.
Vaux08 8rwNormal read/write0x0VAux8 channel.
Vaux07 7rwNormal read/write0x0VAux7 channel.
Vaux06 6rwNormal read/write0x0VAux6 channel.
Vaux05 5rwNormal read/write0x0VAux5 channel.
Vaux04 4rwNormal read/write0x0VAux4 channel.
Vaux03 3rwNormal read/write0x0VAux3 channel.
Vaux02 2rwNormal read/write0x0VAux2 channel.
Vaux01 1rwNormal read/write0x0VAux1 channel.
Vaux00 0rwNormal read/write0x0VAux0 channel.