SEQ_LOW_RATE_CHANNEL1 (PLSYSMON) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SEQ_LOW_RATE_CHANNEL1 (PLSYSMON) Register Description

Register NameSEQ_LOW_RATE_CHANNEL1
Offset Address0x00000001EC
Absolute Address 0x00FFA50DEC (AMS_PL_SYSMON)
Width16
TyperwNormal read/write
Reset Value0x00000000
DescriptionLow-Rate Sequence Channel, Group 1.

SEQ_LOW_RATE_CHANNEL1 (PLSYSMON) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
channel115:0rwNormal read/write0x0Refer to SEQ_CHANNEL1 register for bit assignments.