SICR (APMDDR) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SICR (APMDDR) Register Description

Register NameSICR
Offset Address0x0000000028
Absolute Address 0x00FD0B0028 (APM_DDR)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000100
DescriptionSample Interval Control

SICR (APMDDR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9razRead as zero0x0Reserved
MET_CNT_RST 8rwNormal read/write0x11: Resets metric counters when sample interval timer expires or when the sample register is read. 0: Metric Counters are not reset when sample interval counter lapses or when the sample register is read.
Reserved 7:2razRead as zero0x0Reserved
LOAD 1rwNormal read/write0x01: Loads the Sample Interval register value into the Sample Interval Counter.
ENABLE 0rwNormal read/write0x01: Enables the down counter. Before enabling, the counter should be loaded with the sample Interval Register value.