SNOOP_CTRL (APU) Register Description
| Register Name | SNOOP_CTRL |
|---|---|
| Offset Address | 0x0000000080 |
| Absolute Address | 0x00FD5C0080 (APU) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Snoop Control Register |
SNOOP_CTRL (APU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ACE_inact | 4 | rwNormal read/write | 0x0 | Set this bit to idle the ACE master interface after all snoop transactions have been sent on ACE. |
| ACP_inact | 0 | rwNormal read/write | 0x0 | Set this bit to idle the ACP interface. This indicates that PL sends no more transaction on ACP. When this signal is high, the ACP stops accepting requests by deasserting ARREADYS and AWREADYS. For details, refer to ARM Cortex-A53 MPCore Processor Technical Reference Manual. |