SPER (STM) Register Description
| Register Name | SPER |
|---|
| Offset Address | 0x0000000E00 |
|---|
| Absolute Address |
0x00FE9C0E00 (CORESIGHT_SOC_STM)
|
|---|
| Width | 32 |
|---|
| Type | rwNormal read/write |
|---|
| Reset Value | 0x00000000 |
|---|
| Description | Enable Stimulus Registers to Generate Trace. |
|---|
This read/write only register is used to enable the stimulus registers to generate trace.The register defines one bit per stimulus register. Writing 1 enables the appropriate stimulus port, writing 0 disables the appropriate stimulus port. This register is used in conjunction with the Software Enable Bank Select Register.
SPER (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| SPE | 31:0 | rwNormal read/write | 0x0 | Stimulus port enable, with one bit per stimulus port0 = stimulus port disabled1 = stimulus port enabled |