SPMSCR (STM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SPMSCR (STM) Register Description

Register NameSPMSCR
Offset Address0x0000000E64
Absolute Address 0x00FE9C0E64 (CORESIGHT_SOC_STM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnable a debugger to program which masters the STMSPSCR applies to.

SPMSCR (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
MASTSEL22:15rwNormal read/write0This field defines which master the STMSPSCR applies to
MASTCTL 0rwNormal read/write0x0This defines how the master is applied:
0: Not used.
1: STMSPSCR.