SPTER (STM) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SPTER (STM) Register Description

Register NameSPTER
Offset Address0x0000000E20
Absolute Address 0x00FE9C0E20 (CORESIGHT_SOC_STM)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEnable Trigger Generation on writes to enabled stimulus port registers.

SPTER (STM) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
SPTE31:0rwNormal read/write0x0Bit mask to enable trigger generation from the stimulus port registers, with one bit per stimulus port register0 = disabled1 = enabled