SPTRIGCSR (STM) Register Description
| Register Name | SPTRIGCSR |
|---|---|
| Offset Address | 0x0000000E70 |
| Absolute Address | 0x00FE9C0E70 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Control the STM triggers caused by STMSPTER. |
SPTRIGCSR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ATBTRIGEN_DIR | 4 | rwNormal read/write | 0x0 | When set, this bit enables the STM to use the ATID value of 0x7D when a Trigger Event on writes to TRIG location occurs: 0: disable. 1: enable. |
| ATBTRIGEN_TE | 3 | rwNormal read/write | 0x0 | When set, this bit enables the STM to use the ATID value of 0x7D when a Trigger Event on match using STMSPTER occurs: 0: disable. 1: enable. |
| TRIGCLEAR | 2 | woWrite-only | 0 | When TRIGCTL indicates single-shot mode, this bit is used to clear TRIGSTATUS.Writing a b1 to this bit when in multi-shot mode is Unpredictable: 0: no effect. 1: clear status. |
| TRIGSTATUS | 1 | roRead-only | 0 | When TRIGCTL indicates single-shot mode, this indicates whether the single trigger has occurred: 0: did not occur. 1: occurred. |
| TRIGCTL | 0 | rwNormal read/write | 0x0 | Trigger Control: 0: multi-shot. 1: single-shot. |