SR (R5_ETM_1) Register Description
| Register Name | SR |
|---|---|
| Offset Address | 0x0000000010 |
| Absolute Address | 0x00FEBFD010 (CORESIGHT_R5_ETM_1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000002 |
| Description | Status Register |
SR (R5_ETM_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Trigger | 3 | rwNormal read/write | 0x0 | Trigger bit. Set when the trigger occurs, and prevents the trigger from being output until the ETM is next programmed. |
| Status | 2 | rwNormal read/write | 0x0 | Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match. |
| Programming | 1 | roRead-only | 0x1 | The current effective value of the ETM Programming bit (ETM Control Register bit [10]). You must wait for this bit to go to 1 before you start to program the ETM. If you read other bits in the ETM Status Register while this bit is 0, some instructions might not have taken effect. It is recommended that you set the ETM Programming bit and wait for this bit to go to 1 before reading the overflow bit. This bit remains 0 if there is any data in the FIFO. This ensures that the FIFO is empty before the ETM programming is changed. |
| Overflow | 0 | roRead-only | 0x0 | If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either: - trace is restarted. - the ETM Power Down bit, bit [0] of the ETM Control Register, 0x00, is set to 1. Note: Setting or clearing the ETM Programming bit does not cause this bit to be cleared. |