SRR (CAN) Register Description
| Register Name | SRR |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FF060000 (CAN0) 0x00FF070000 (CAN1) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Software Reset and Enable |
Writing to the Software Reset Register (SRR) places the CAN controller in Configuration mode. Once in Configuration mode, the CAN controller drives recessive on the bus line and does not transmit or receive messages. During power-up, CEN and SRST bits are 0 and CONFIG bit in the Status Register (SR) is 1. The Transfer Layer Configuration Registers can be changed only when CEN bit in the SRR Register is 0. If the CEN bit is changed during core operation, it is recommended to reset the core so that operations start afresh.
SRR (CAN) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:2 | rwNormal read/write | 0x0 | Reserved. |
| CEN | 1 | rwNormal read/write | 0x0 | CAN Enable The Enable bit for the CAN controller. 1: The CAN controller is in loopback, Sleep or Normal mode depending on the LBACK and SLEEP bits in the MSR. 0: The CAN controller is in the Configuration mode. If the CEN bit is changed during core operation, it is recommended to reset the core so that operations start afresh. |
| SRST | 0 | rwNormal read/write | 0x0 | Reset The Software reset bit for the CAN controller. 1: CAN controller is reset. If a 1 is written to this bit, all the CAN controller configuration registers (including the SRR) are reset. Reads to this bit always return a 0. |