STALLCTLR (A53_ETM_0) Register Description
Register Name | STALLCTLR |
---|---|
Offset Address | 0x000000002C |
Absolute Address | 0x00FEC4002C (CORESIGHT_A53_ETM_0) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | Stall Control Register |
STALLCTLR (A53_ETM_0) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
ISTALL | 8 | rwNormal read/write | 0x0 | Instuction stall bit. Controls if the trace unit can stall the processor when the instruction trace buffer space is less then LEVEL |
LEVEL | 3:2 | rwNormal read/write | 0x0 | Thereshold level field. The field can support 4 monotonic levels from 0b00 to 0b11, where: 0b00: Zero invations. This setting has a greater risk of an ETM trace unit FIFO overflow 0b11: Maximum invations occurs but there is less risk of a FIFO overflow |