STALLCTLR (A53_ETM_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

STALLCTLR (A53_ETM_2) Register Description

Register NameSTALLCTLR
Offset Address0x000000002C
Absolute Address 0x00FEE4002C (CORESIGHT_A53_ETM_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionStall Control Register

STALLCTLR (A53_ETM_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ISTALL 8rwNormal read/write0x0Instuction stall bit.
Controls if the trace unit can stall the processor when the instruction trace buffer space is less then LEVEL
LEVEL 3:2rwNormal read/write0x0Thereshold level field.
The field can support 4 monotonic levels from 0b00 to 0b11, where:
0b00: Zero invations.
This setting has a greater risk of an ETM trace unit FIFO overflow
0b11: Maximum invations occurs but there is less risk of a FIFO overflow