STATUS (EFUSE) Register Description
| Register Name | STATUS |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address | 0x00FFCC0008 (EFUSE) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Status |
STATUS (EFUSE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| AES_CRC_PASS | 7 | roRead-only | 0x0 | Indicates that the AES key integrity check passed. This bit is only valid when AES_CRC_DONE is set. |
| AES_CRC_DONE | 6 | roRead-only | 0x0 | Indicates that the AES key integrity chck has finished. Pass/Fail is indicated in the AES_CRC_PASS bit. |
| CACHE_DONE | 5 | roRead-only | 0x0 | Indicates that the EFUSE Cache has completed loading |
| CACHE_LOAD | 4 | roRead-only | 0x0 | Indicates that the EFUSE Cache is currently being loaded. |
| Reserved | 3 | roRead-only | 0x0 | Reserved |
| efuse_0_tbit | 0 | roRead-only | 0x0 | Indicates if the TBIT pattern was successfully read from eFuse 0. If the TBIT pattern fails, RSA Authentication and AES eFuse key are disabled. 0: fail 1: pass |