STM Module Description
| Module Name | STM Module |
|---|---|
| Modules of this Type | CORESIGHT_SOC_STM |
| Base Addresses | 0x00FE9C0000 (CORESIGHT_SOC_STM) |
| Description | System Trace Macrocell |
STM Module Register Summary
| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| DMASTARTR | 0x0000000C04 | 32 | woWrite-only | 0x00000000 | Start DMA Transfer. |
| DMASTOPR | 0x0000000C08 | 32 | woWrite-only | 0x00000000 | Stop DMA Transfer. |
| DMASTATR | 0x0000000C0C | 32 | roRead-only | 0x00000000 | DMA Transfer Status. |
| DMACTLR | 0x0000000C10 | 32 | rwNormal read/write | 0x00000000 | Controls the DMA transfer request mechanism. |
| DMAIDR | 0x0000000CFC | 32 | roRead-only | 0x00000000 | DMA features of the STM (read-only). |
| HEER | 0x0000000D00 | 32 | rwNormal read/write | 0x00000000 | Enable Hardware Events for Trace |
| HETER | 0x0000000D20 | 32 | rwNormal read/write | 0x00000000 | Enable Trigger Generation on Hardware Events. |
| HEBSR | 0x0000000D60 | 32 | rwNormal read/write | 0x00000000 | Select the Hardware Event bank. |
| HEMCR | 0x0000000D64 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Control the primary functions of Hardware Event tracing. |
| HEEXTMUXR | 0x0000000D68 | 32 | rwNormal read/write | 0x00000000 | Control hardware event multiplexors external to STM. |
| HEMASTR | 0x0000000DF4 | 32 | roRead-only | 0x00000000 | Master Number in Event Trace |
| HEFEAT1R | 0x0000000DF8 | 32 | roRead-only | 0x00000000 | Read the features of the STM. |
| HEIDR | 0x0000000DFC | 32 | roRead-only | 0x00000000 | Read the features of hardware event tracing in STM. |
| SPER | 0x0000000E00 | 32 | rwNormal read/write | 0x00000000 | Enable Stimulus Registers to Generate Trace. |
| SPTER | 0x0000000E20 | 32 | rwNormal read/write | 0x00000000 | Enable Trigger Generation on writes to enabled stimulus port registers. |
| SPSCR | 0x0000000E60 | 32 | rwNormal read/write | 0x00000000 | Enable a debugger to program which stimulus ports the STMSPER and STMSPTER apply to. |
| SPMSCR | 0x0000000E64 | 32 | rwNormal read/write | 0x00000000 | Enable a debugger to program which masters the STMSPSCR applies to. |
| SPOVERRIDER | 0x0000000E68 | 32 | rwNormal read/write | 0x00000000 | Enable a debugger to override various features of the STM. |
| SPMOVERRIDER | 0x0000000E6C | 32 | rwNormal read/write | 0x00000000 | Enables a debugger to choose which masters the STMSPOVERRIDERR applies to. |
| SPTRIGCSR | 0x0000000E70 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Control the STM triggers caused by STMSPTER. |
| TCSR | 0x0000000E80 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Controls the STM settings. |
| TSSTIMR | 0x0000000E84 | 32 | woWrite-only | 0x00000000 | Force Timestamp Output. |
| TSFREQR | 0x0000000E8C | 32 | rwNormal read/write | 0x00000000 | Timestamp Counter Frequency. |
| SYNCR | 0x0000000E90 | 32 | rwNormal read/write | 0x00000000 | Interval Between Synchronization Packets. |
| AUXCR | 0x0000000E94 | 32 | rwNormal read/write | 0x00000000 | Implementation Defined STM controls. |
| FEAT1R | 0x0000000EA0 | 32 | roRead-only | 0x00000000 | Read the features of the STM. |
| FEAT2R | 0x0000000EA4 | 32 | roRead-only | 0x00000000 | Read the features of the STM. |
| FEAT3R | 0x0000000EA8 | 32 | roRead-only | 0x00000000 | Indicates the features of the STM. |
| ITTRIGGER | 0x0000000EE8 | 32 | woWrite-only | 0x00000000 | Integration Test for Cross-Trigger Outputs. |
| ITATBDATA0 | 0x0000000EEC | 32 | woWrite-only | 0x00000000 | Control the value of the ATDATAM outputs in integration mode. |
| ITATBCTR2 | 0x0000000EF0 | 32 | roRead-only | 0x00000000 | Return value of the ATREADYM and AFVALIDM inputs in integration mode. |
| ITATBID | 0x0000000EF4 | 32 | woWrite-only | 0x00000000 | Control value of the ATIDM output in integration mode. |
| ITATBCTR0 | 0x0000000EF8 | 32 | woWrite-only | 0x00000000 | Control value of the ATVALIDM, AFREADYM, and ATBYTESM outputs in integration mode. |
| ITCTRL | 0x0000000F00 | 32 | rwNormal read/write | 0x00000000 | Enable Topology Detection. |
| CLAIMSET | 0x0000000FA0 | 32 | woWrite-only | 0x0000000F | Claim Tag Set. |
| CLAIMCLR | 0x0000000FA4 | 32 | woWrite-only | 0x00000000 | Claim Tag Clear. |
| LAR | 0x0000000FB0 | 32 | woWrite-only | 0x00000000 | Enables write access to device registers. |
| LSR | 0x0000000FB4 | 32 | roRead-only | 0x00000000 | Status of Lock Control Mechanism. |
| AUTHSTATUS | 0x0000000FB8 | 32 | roRead-only | 0x000000AA | Reports the required security level and current status of the authentication interface. |
| DEVARCH | 0x0000000FBC | 32 | roRead-only | 0x00000000 | Indicates the architect and architecture of the STM. For the STM-500, the architect is Arm, and the architecture is STMv1.1 |
| DEVID | 0x0000000FC8 | 32 | roRead-only | 0x00000000 | Indicates the capabilities of the CoreSight STM. |
| DEVTYPE | 0x0000000FCC | 32 | roRead-only | 0x00000000 | Type Classification. |
| PIDR4 | 0x0000000FD0 | 32 | roRead-only | 0x00000000 | PID - Designer Identity and Memory Footprint. |
| PIDR5 | 0x0000000FD4 | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR6 | 0x0000000FD8 | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR7 | 0x0000000FDC | 32 | roRead-only | 0x00000000 | Reserved |
| PIDR0 | 0x0000000FE0 | 32 | roRead-only | 0x00000000 | PID - Designer Part Number |
| PIDR1 | 0x0000000FE4 | 32 | roRead-only | 0x00000000 | PID - Part Number and Designer Identify. |
| PIDR2 | 0x0000000FE8 | 32 | roRead-only | 0x0000001B | PID - Design Identity and Product Revision. |
| PIDR3 | 0x0000000FEC | 32 | roRead-only | 0x00000000 | PID - RevAnd and Customer-modified Bit Fields. |
| CIDR0 | 0x0000000FF0 | 32 | roRead-only | 0x00000000 | CID - Indentification Registers Present. |
| CIDR1 | 0x0000000FF4 | 32 | roRead-only | 0x00000000 | CID - Indentification Registers Present and Component Class. |
| CIDR2 | 0x0000000FF8 | 32 | roRead-only | 0x00000005 | CID - Indentification Registers Present. |
| CIDR3 | 0x0000000FFC | 32 | roRead-only | 0x00000000 | CID - Indentification Registers Present. |