SWINC_EL0 (A53_PMU_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SWINC_EL0 (A53_PMU_1) Register Description

Register NameSWINC_EL0
Offset Address0x0000000CA0
Absolute Address 0x00FED30CA0 (CORESIGHT_A53_PMU_1)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionPerformance Monitors Software Increment Register

SWINC_EL0 (A53_PMU_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P30:0woWrite-only0Event counter software increment bit for EVCNTR<x>.P<x> is WI if x >= PMCR_EL0.N, the number of implemented counters.Otherwise, the effects of writing to this bit are: