SYNCR (STM) Register Description
| Register Name | SYNCR |
|---|---|
| Offset Address | 0x0000000E90 |
| Absolute Address | 0x00FE9C0E90 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Interval Between Synchronization Packets. |
This register controls the interval between synchronization packets, in terms of the number of bytes of trace generated.This register only provides a hint of the desired synchronization frequency, implementations are permitted to be inaccurate. Writing a value of 0x00000000 to this register disables the synchronization counter however any other IMPLEMENTATION DEFINED synchronizations mechanism continue to operate independently.
SYNCR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| MODE | 12 | rwNormal read/write | 0x0 | Mode control: 0: N bytes. 1: 2^N bytes. |
| COUNT | 11:3 | rwNormal read/write | 0x0 | Counter value for the number of bytes between synchronization packets. Reads return the value of this register. |