Supported_trigger_modes (TPIU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Supported_trigger_modes (TPIU) Register Description

Register NameSupported_trigger_modes
Offset Address0x0000000100
Absolute Address 0x00FE980100 (CORESIGHT_SOC_TPIU)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionThis register indicates the implemented Trigger Counter multipliers and other supported features of the trigger system.

Supported_trigger_modes (TPIU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TrgRun17roRead-only0x0A trigger has occurred but the counter is not at zero.
TRIGGERED16roRead-only0x0A trigger has occurred and the counter has reached zero.
TCOUNT8 8roRead-only0x0Indicates whether an 8-bit wide counter register implemented.
MULT64K 4roRead-only0x0Indicates whether multiply the Trigger Counter by 65536 is supported.
MULT256 3roRead-only0x0Indicates whether multiply the Trigger Counter by 256 is supported.
MULT16 2roRead-only0x0Indicates whether multiply the Trigger Counter by 16 is supported.
MULT4 1roRead-only0x0Indicates whether multiply the Trigger Counter by 4 is supported.
MULT2 0roRead-only0x0Indicates whether multiply the Trigger Counter by 2 is supported.