TCMTR (R5_DBG_1) Register Description
| Register Name | TCMTR |
|---|---|
| Offset Address | 0x0000000D08 |
| Absolute Address | 0x00FEBF2D08 (CORESIGHT_R5_DBG_1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00010001 |
| Description | TCM Type Register |
TCMTR (R5_DBG_1) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| format | 31:29 | roRead-only | 0x0 | Always 0, indicating v6 format TCMTR. |
| BTCM | 18:16 | roRead-only | 0x1 | Specifies the number of BTCMs implemented. This is always set to 001 because the processor has one BTCM. |
| ATCM | 2:0 | roRead-only | 0x1 | Specifies the number of ATCMs implemented. Always set to 001. The processor has one ATCM |