TCSR (STM) Register Description
| Register Name | TCSR |
|---|---|
| Offset Address | 0x0000000E80 |
| Absolute Address | 0x00FE9C0E80 (CORESIGHT_SOC_STM) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Controls the STM settings. |
TCSR (STM) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| BUSY | 23 | roRead-only | 0x0 | STM is busy, for example the STM trace FIFO is not empty: 0: idle. 1: busy. |
| TRACEID | 22:16 | rwNormal read/write | 0 | ATB Trace ID. |
| COMPEN | 5 | rwNormal read/write | 0x0 | Compression Enable for Stimulus Ports: 0: disable. 1: enable. |
| SYNCEN | 2 | roRead-only | 0x0 | STMSYNCR is implemented so this value is RAO. |
| TSEN | 1 | rwNormal read/write | 0x0 | Controls if timestamp requests are ignored or not: 0: disable. 1: enable. |
| EN | 0 | rwNormal read/write | 0x0 | Global STM enable: 0: disable. 1: enable. |