TECR1 (R5_ETM_0) Register Description
| Register Name | TECR1 |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address | 0x00FEBFC024 (CORESIGHT_R5_ETM_0) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | TraceEnable Control1 Register |
TECR1 (R5_ETM_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Start_stop_enable | 25 | rwNormal read/write | 0 | Trace start/stop enable. The possible values of this bit are: 0: Tracing is unaffected by the trace start/stop logic. 1: Tracing is controlled by the trace on and off addresses configured for the trace start/stop logic. The trace start/stop resource (resource 0x5F) is unaffected by the value of this bit. |
| Inc_Exc_control | 24 | rwNormal read/write | 0 | Include/exclude control. The possible values of this bit are: 0: Include. The specified resources indicate the regions where tracing can occur. When outside this region tracing is prevented. 1: Exclude. The resources, specified in bits [23:0] and in the TraceEnable Control 2 Register, indicate regions to be excluded from the trace. When outside an exclude region, tracing can occur. |
| Mmap_select | 23:8 | rwNormal read/write | 0 | When a bit is set to 1, it selects memory map decode 16-1 for include/exclude control. For example, bit [8] set to 1 selects MMD 1. |
| Rangecmp_select | 7:0 | rwNormal read/write | 0 | When a bit is set to 1, it selects address range comparator 8-1 for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1. |