TECR2 (R5_ETM_0) Register Description
| Register Name | TECR2 |
|---|---|
| Offset Address | 0x000000001C |
| Absolute Address | 0x00FEBFC01C (CORESIGHT_R5_ETM_0) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | TraceEnable Control 2 Register |
TECR2 (R5_ETM_0) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Addrcmp_select | 15:0 | rwNormal read/write | 0 | When a bit is set to 1, it selects a single address comparator 16-1 for include/exclude control. For example, bit [0] set to 1 selects single address comparator 1. |