TPIU Module

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TPIU Module Description

Module NameTPIU Module
Modules of this TypeCORESIGHT_SOC_TPIU
Base Addresses 0x00FE980000 (CORESIGHT_SOC_TPIU)
DescriptionTrace Port Interface Unit

TPIU Module Register Summary

Register NameOffset AddressWidthTypeReset ValueDescription
Supported_Port_Sizes0x000000000032roRead-only0x00000000Each bit location represents a single port size that is supported on the device, that is, 32-1 in bit locations [31:0].
Current_port_size0x000000000432rwNormal read/write0x00000000The Current Port Size Register has the same format as the Supported Port Sizes register but only one bit is set, and all others must be zero. Writing values with more than one bit set or setting a bit that is not indicated as supported is not supported and causes unpredictable behavior.On reset this defaults to the smallest possible port size, 1 bit, and so reads as 0x00000001.Note: Do not modify the value while the Trace Port is still active, or without correctly stopping the formatter (see Formatter and Flush Control Register, 0x304). This can result in data not being aligned to the port width. For example, data on an 8-bit Trace Port might not be byte aligned.
Supported_trigger_modes0x000000010032roRead-only0x00000000This register indicates the implemented Trigger Counter multipliers and other supported features of the trigger system.
Trigger_counter_value0x000000010432rwNormal read/write0x00000000The Trigger Counter Register enables delaying the indication of triggers to any external connected trace capture or storage devices. This counter is only eight bits wide and is intended to only be used with the counter multipliers in the Trigger Multiplier Register, 0x108. When a trigger is started, this value, in combination with the multiplier, is the number of words before the trigger is indicated. When the trigger counter reaches zero, the value written here is reloaded. Writing to this register causes the trigger counter value to reset but not reset any values on the multiplier. Reading this register returns the preset value not the current count.
Trigger_multiplier0x000000010832rwNormal read/write0x00000000This register contains the selectors for the Trigger Counter Multiplier. Several multipliers can be selected to create the required multiplier value, that is, any value between 1 and approximately 2x10^9. The default value is multiplied by 1, 0x0.Writing to this register causes the internal trigger counter and the state in the multipliers to be reset to initial count position, that is, trigger counter is reloaded with the Trigger Counter Register value and all multipliers are reset.
Supported_test_pattern_modes0x000000020032roRead-only0x00000000The pattern generator unit provides a set of known bit sequences or patterns that can be output over the Trace Port and be detected by the TPA or other associated trace capture device.
Current_test_pattern_mode0x000000020432rwNormal read/write0x00000000This register indicates the current test pattern/mode selected. Only one of the modes can be set, using bits 17-16, but a multiple number of bits for the patterns can be set using bits 3-0. If Timed Mode is chosen, then after the allotted number of cycles has been reached, the mode automatically switches to Off Mode. On reset this register is set to 18h00000, Off Mode with no selected patterns.
TPRCR0x000000020832rwNormal read/write0x00000000This is an eight-bit counter start value that is decremented. A write sets the initial counter value and a read returns the programmed value. On reset this value is set to 0.
FFSR0x000000030032roRead-only0x00000000This register indicates the current status of the formatter and flush features available in the TPIU.
FFCR0x000000030432rwNormal read/write0x00000000This register controls the generation of stop, trigger, and flush events.To disable formatting and put the formatter into bypass mode, bits 1 and 0 must be clear. Setting both bits is the same as setting bit 1.All three flush generating conditions can be enabled together. However, if a second or third flush event is generated from another condition then the current flush completes before the next flush is serviced. Flush from flushin takes priority over flush from Trigger, which in turn completes before a manually activated flush. All Trigger indication conditions can be enabled simultaneously although this can cause the appearance of multiple triggers if flush using trigger is also enabled.Both Stop On settings can be enabled, although if flush on trigger is set up then none of the flushed data is stored. When the system stops, it returns atreadys and does not store the accepted data packets. This is to avoid stalling of any other devices that are connected to a Trace Replicator.If an event in the Formatter and Flush Control Register is required, it must be enabled before the originating event starts. Because requests from flushes and triggers can originate in an asynchronous clock domain, the exact time the component acts on the request cannot be determined with respect to configuring the control.Note - It is recommended that the Trace Port width is changed without enabling continuous mode. Enabling continuous mode causes data to be output from the Trace Port and modifying the port size can result in data not being aligned for power2 port widths.- To perform a stop on flush completion through a manually-generated flush request, two write operations to the register are required: one to enable the stop event, if it is not already enabled; one to generate the manual flush.
FSCR0x000000030832rwNormal read/write0x00000040The Formatter Synchronization Counter Register enables effective use on different sized Trace Port Analyzers (TPAs) without wasting large amounts of the storage capacity of the capture device.This counter is the number of formatter frames since the last synchronization packet of 128 bits, and is a 12-bit counter with a maximum count value of 4096. This equates to synchronization every 65536 bytes, that is, 4096 packets x 16 bytes per packet. The default is set up for a synchronization packet every 1024 bytes, that is, every 64 formatter frames.If the formatter has been configured for continuous mode, full and half-word sync frames are inserted during normal operation. Under these circumstances the count value represents the maximum number of complete frames between full synchronization packets.
EXTCTL_In_Port0x000000040032roRead-only0x00000000Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexors or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. The output register bank is set to all zeros on reset. The input registers sample the incoming signals and as such are undefined.
EXTCTL_Out_Port0x000000040432rwNormal read/write0x00000000Two ports can be used as a control and feedback mechanism for any serializers, pin sharing multiplexors or other solutions that might be added to the trace output pins either for pin control or a high speed trace port solution. These ports are raw register banks that sample or export the corresponding external pins. The output register bank is set to all zeros on reset. The input registers sample the incoming signals and as such are undefined.
ITTRFLINACK0x0000000EE432woWrite-only0x00000000The Integration Test Trigger In and Flush In Acknowledge Register enables control of the triginack and flushinack outputs from the TPIU.
ITTRFLIN0x0000000EE832roRead-only0x00000000The Integration Test Trigger In and Flush In Register contains the values of the flushin and trigin inputs to the TPIU.
ITATBDATA00x0000000EEC32roRead-only0x00000000The Integration Test ATB Data Register 0 contains the value of the atdatas inputs to the TPIU. The values are only valid when atvalids is HIGH.
ITATBCTR20x0000000EF032woWrite-only0x00000000The Integration Test ATB Control Register 2 enables control of the atreadys and afvalids outputs of the TPIU.
ITATBCTR10x0000000EF432roRead-only0x00000000The Integration Test ATB Control Register 1 contains the value of the atids input to the TPIU. This is only valid when atvalids is HIGH.
ITATBCTR00x0000000EF832roRead-only0x00000000The Integration Test ATB Control Register 0 captures the values of the atvalids, afreadys, and atbytess inputs to the TPIU. To ensure the integration registers work correctly in a system, the value of atbytess is only valid when atvalids, bit [0], is HIGH.
ITCTRL0x0000000F0032rwNormal read/write0x00000000This register is used to enable topology detection. For more information see the CoreSight Architecture Specification. This register enables the component to switch from a functional mode, the default behavior, to integration mode where the inputs and outputs of the component can be directly controlled for the purpose of integration testing and topology solving. Note: When a device has been in integration mode, it might not function with the original behavior. After performing integration or topology detection, you must reset the system to ensure correct behavior of CoreSight and other connected system components that are affected by the integration or topology detection.The registers in the TPIU enable the system to set the flushinack and triginack output pins. The flushin and trigin inputs to the TPIU can also be read. The other Integration Test Registers are for testing the integration of the ATB slave interface on the TPIU.
CLAIMSET0x0000000FA032rwNormal read/write0x00000000This is used in conjunction with Claim Tag Clear Register, CLAIMCLR. This register forms one half of the Claim Tag value. This location allows individual bits to be set, write, and returns the number of bits that can be set, read.
CLAIMCLR0x0000000FA432rwNormal read/write0x00000000This register is used in conjunction with Claim Tag Set Register, CLAIMSET. This register forms one half of the Claim Tag value. This location enables individual bits to be cleared, write, and returns the current Claim Tag value, read.
LAR0x0000000FB032woWrite-only0x00000000This is used to enable write access to device registers. External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. A debugger does not have to unlock the component in order to write and modify the registers in the component.
LSR0x0000000FB432roRead-only0x00000000This indicates the status of the Lock control mechanism. This lock prevents accidental writes by code under debug. When locked, write access is blocked to all registers, except the Lock Access Register.External accesses from a debugger (paddrdbg31 = 1) are not subject to the Lock Registers. This register reads as 0 when read from an external debugger (paddrdbg31 = 1).
AUTHSTATUS0x0000000FB832roRead-only0x00000000Reports what functionality is currently permitted by the authentication interface.
DEVID0x0000000FC832roRead-only0x00000000This register indicates the capabilities of the TPIU.
DEVTYPE0x0000000FCC32roRead-only0x00000000It provides a debugger with information about the component when the Part Number field is not recognized. The debugger can then report this information.
PIDR40x0000000FD032roRead-only0x00000000Part of the set of Peripheral Identification registers. Contains part of the designer identity and the memory footprint indicator.
PIDR50x0000000FD432rwNormal read/write0x00000000Reserved
PIDR60x0000000FD832rwNormal read/write0x00000000Reserved
PIDR70x0000000FDC32rwNormal read/write0x00000000Reserved
PIDR00x0000000FE032roRead-only0x00000000Part of the set of Peripheral Identification registers. Contains part of the designer specific part number.
PIDR10x0000000FE432roRead-only0x00000000Part of the set of Peripheral Identification registers. Contains part of the designer specific part number and part of the designer identity.
PIDR20x0000000FE832roRead-only0x00000000Part of the set of Peripheral Identification registers. Contains part of the designer identity and the product revision.
PIDR30x0000000FEC32roRead-only0x00000000Part of the set of Peripheral Identification registers. Contains the RevAnd and Customer Modified fields.
CIDR00x0000000FF032roRead-only0x00000000A component identification register, that indicates that the identification registers are present.
CIDR10x0000000FF432roRead-only0x00000000A component identification register, that indicates that the identification registers are present. This register also indicates the component class.
CIDR20x0000000FF832roRead-only0x00000000A component identification register, that indicates that the identification registers are present.
CIDR30x0000000FFC32roRead-only0x00000000A component identification register, that indicates that the identification registers are present.