TRACEIDR (A53_ETM_3) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TRACEIDR (A53_ETM_3) Register Description

Register NameTRACEIDR
Offset Address0x0000000040
Absolute Address 0x00FEF40040 (CORESIGHT_A53_ETM_3)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTrace ID Register

TRACEIDR (A53_ETM_3) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TRACEID31:0rwNormal read/write0x0Trace ID field. Sets the trace ID value for instruction trace.Bit[0] must be zero if data trace is enabled. If data trace is enabled then a trace unit sets the trace ID for data trace, to TRACEID+1.Bits [31:N] are RAZ/WI, where N is the value of IDR5.TRACEIDSIZE.If an implementation supports the CoreSight AMBA Trace Bus (ATB) then:The width of the field is 7 bits.Writing a reserved trace ID value causes UNPREDICTABLE behavior. See the AMBA 3 ATB Protocol Specification for information about which ATID bus values are reserved.