TRAN_EGRESS_CAPABILITIES (AXIPCIE_EGRESS) Register Description
| Register Name | TRAN_EGRESS_CAPABILITIES |
|---|---|
| Offset Address | 0x0000000000 |
| Absolute Address |
0x00FD0E0C00 (AXIPCIE_EGRESS0) 0x00FD0E0C20 (AXIPCIE_EGRESS1) 0x00FD0E0C40 (AXIPCIE_EGRESS2) 0x00FD0E0C60 (AXIPCIE_EGRESS3) 0x00FD0E0C80 (AXIPCIE_EGRESS4) 0x00FD0E0CA0 (AXIPCIE_EGRESS5) 0x00FD0E0CC0 (AXIPCIE_EGRESS6) 0x00FD0E0CE0 (AXIPCIE_EGRESS7) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x1F0C0001 |
| Description | Egress AXI Translation - Capabilities |
TRAN_EGRESS_CAPABILITIES (AXIPCIE_EGRESS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| egress_size_max | 31:24 | roRead-only | 0x1F | * egress_size supports values between 0 and egress_size_max. * Maximum translation size is 2^(egress_size_offset+egress_size_max). |
| egress_size_offset | 23:16 | roRead-only | 0xC | Minimum translation size is 2^(egress_size_offset). |
| Reserved | 15:1 | roRead-only | 0x0 | |
| egress_present | 0 | roRead-only | 0x1 | Translation presence indicator. |