TRAN_EGRESS_CONTROL (AXIPCIE_EGRESS) Register Description
Register Name | TRAN_EGRESS_CONTROL |
---|---|
Offset Address | 0x0000000008 |
Absolute Address |
0x00FD0E0C08 (AXIPCIE_EGRESS0) 0x00FD0E0C28 (AXIPCIE_EGRESS1) 0x00FD0E0C48 (AXIPCIE_EGRESS2) 0x00FD0E0C68 (AXIPCIE_EGRESS3) 0x00FD0E0C88 (AXIPCIE_EGRESS4) 0x00FD0E0CA8 (AXIPCIE_EGRESS5) 0x00FD0E0CC8 (AXIPCIE_EGRESS6) 0x00FD0E0CE8 (AXIPCIE_EGRESS7) |
Width | 32 |
Type | mixedMixed types. See bit-field details. |
Reset Value | 0x00000000 |
Description | Egress AXI Translation - Control |
TRAN_EGRESS_CONTROL (AXIPCIE_EGRESS) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
egress_attr_w | 31:28 | rwNormal read/write | 0x0 | Egress Write Attribute Override. When egress_attr_enable == 1, the PCIe attributes {ID Based Ordering, Relaxed Ordering, No Snoop} are set to egress_attr_w[2:0] when forwarding write transactions hitting this translation to PCIe. When egress_attr_enable == 0, PCIe attributes are all set to 0 when forwarding write transactions hitting this translation to PCIe. Attributes which are not allowed to be set due to PCI Express Configuration Register enable functionality will be cleared before the transaction is forwarded to PCIe. |
egress_attr_r | 27:24 | rwNormal read/write | 0x0 | Egress Read Attribute Override. When egress_attr_enable == 1, the PCIe attributes {ID Based Ordering, Relaxed Ordering, No Snoop} are set to egress_attr_r[2:0] when forwarding read transactions hitting this translation to PCIe. When egress_attr_enable == 0, PCIe attributes are all set to 0 when forwarding read transactions hitting this translation to PCIe. Attributes which are not allowed to be set due to PCI Express Configuration Register enable functionality will be cleared before the transaction is forwarded to PCIe. |
egress_attr_enable | 23 | rwNormal read/write | 0x0 | Egress Write/Read Attribute Override Enable. |
Reserved | 22:21 | roRead-only | 0x0 | |
egress_size | 20:16 | rwNormal read/write | 0x0 | Translation Size. The translation window size in bytes is configured to be 2^(egress_size_offset+egress_size). egress_size must be <= egress_size_max. |
Reserved | 15:14 | roRead-only | 0x0 | |
Reserved | 13:8 | roRead-only | 0x0 | |
Reserved | 7:5 | roRead-only | 0x0 | |
Reserved | 4 | roRead-only | 0x0 | |
egress_invalid | 3 | rwNormal read/write | 0x0 | Translation Invalidate Enable. |
egress_security_enable | 2 | rwNormal read/write | 0x0 | Translation Security Enable. |
Reserved | 1 | roRead-only | 0x0 | |
egress_enable | 0 | rwNormal read/write | 0x0 | Translation Enable. The translation is hit when both of the following are true: * egress_enable == 1 * egress_src_base[63:(12+egress_size)] == AXI Address[63:(12+egress_size)] |