TRAN_EGRESS_CONTROL (AXIPCIE_EGRESS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TRAN_EGRESS_CONTROL (AXIPCIE_EGRESS) Register Description

Register NameTRAN_EGRESS_CONTROL
Offset Address0x0000000008
Absolute Address 0x00FD0E0C08 (AXIPCIE_EGRESS0)
0x00FD0E0C28 (AXIPCIE_EGRESS1)
0x00FD0E0C48 (AXIPCIE_EGRESS2)
0x00FD0E0C68 (AXIPCIE_EGRESS3)
0x00FD0E0C88 (AXIPCIE_EGRESS4)
0x00FD0E0CA8 (AXIPCIE_EGRESS5)
0x00FD0E0CC8 (AXIPCIE_EGRESS6)
0x00FD0E0CE8 (AXIPCIE_EGRESS7)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionEgress AXI Translation - Control

TRAN_EGRESS_CONTROL (AXIPCIE_EGRESS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
egress_attr_w31:28rwNormal read/write0x0Egress Write Attribute Override. When egress_attr_enable == 1, the PCIe attributes {ID Based Ordering, Relaxed Ordering, No Snoop} are set to egress_attr_w[2:0] when forwarding write transactions hitting this translation to PCIe. When egress_attr_enable == 0, PCIe attributes are all set to 0 when forwarding write transactions hitting this translation to PCIe. Attributes which are not allowed to be set due to PCI Express Configuration Register enable functionality will be cleared before the transaction is forwarded to PCIe.
egress_attr_r27:24rwNormal read/write0x0Egress Read Attribute Override. When egress_attr_enable == 1, the PCIe attributes {ID Based Ordering, Relaxed Ordering, No Snoop} are set to egress_attr_r[2:0] when forwarding read transactions hitting this translation to PCIe. When egress_attr_enable == 0, PCIe attributes are all set to 0 when forwarding read transactions hitting this translation to PCIe. Attributes which are not allowed to be set due to PCI Express Configuration Register enable functionality will be cleared before the transaction is forwarded to PCIe.
egress_attr_enable23rwNormal read/write0x0Egress Write/Read Attribute Override Enable.
Reserved22:21roRead-only0x0
egress_size20:16rwNormal read/write0x0Translation Size. The translation window size in bytes is configured to be 2^(egress_size_offset+egress_size). egress_size must be <= egress_size_max.
Reserved15:14roRead-only0x0
Reserved13:8roRead-only0x0
Reserved 7:5roRead-only0x0
Reserved 4roRead-only0x0
egress_invalid 3rwNormal read/write0x0Translation Invalidate Enable.
egress_security_enable 2rwNormal read/write0x0Translation Security Enable.
Reserved 1roRead-only0x0
egress_enable 0rwNormal read/write0x0Translation Enable. The translation is hit when both of the following are true:
* egress_enable == 1
* egress_src_base[63:(12+egress_size)] == AXI Address[63:(12+egress_size)]