TRAN_EGRESS_SRC_BASE_HI (AXIPCIE_EGRESS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TRAN_EGRESS_SRC_BASE_HI (AXIPCIE_EGRESS) Register Description

Register NameTRAN_EGRESS_SRC_BASE_HI
Offset Address0x0000000014
Absolute Address 0x00FD0E0C14 (AXIPCIE_EGRESS0)
0x00FD0E0C34 (AXIPCIE_EGRESS1)
0x00FD0E0C54 (AXIPCIE_EGRESS2)
0x00FD0E0C74 (AXIPCIE_EGRESS3)
0x00FD0E0C94 (AXIPCIE_EGRESS4)
0x00FD0E0CB4 (AXIPCIE_EGRESS5)
0x00FD0E0CD4 (AXIPCIE_EGRESS6)
0x00FD0E0CF4 (AXIPCIE_EGRESS7)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionEgress AXI Translation - Source Address High

TRAN_EGRESS_SRC_BASE_HI (AXIPCIE_EGRESS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
egress_src_base_hi31:0rwNormal read/write0x0egress_src_base[63:32].