TRAN_EGRESS_STATUS (AXIPCIE_EGRESS) Register Description
| Register Name | TRAN_EGRESS_STATUS |
|---|---|
| Offset Address | 0x0000000004 |
| Absolute Address |
0x00FD0E0C04 (AXIPCIE_EGRESS0) 0x00FD0E0C24 (AXIPCIE_EGRESS1) 0x00FD0E0C44 (AXIPCIE_EGRESS2) 0x00FD0E0C64 (AXIPCIE_EGRESS3) 0x00FD0E0C84 (AXIPCIE_EGRESS4) 0x00FD0E0CA4 (AXIPCIE_EGRESS5) 0x00FD0E0CC4 (AXIPCIE_EGRESS6) 0x00FD0E0CE4 (AXIPCIE_EGRESS7) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Egress AXI Translation - Status |
TRAN_EGRESS_STATUS (AXIPCIE_EGRESS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:25 | roRead-only | 0x0 | |
| wr_pending_ctr | 24:16 | roRead-only | 0x0 | Number of write transactions outstanding for this translation. There cannot be more translations outstanding than the number of simultaneously outstanding transactions supported by the Expresso DMA Core (which is always <512 transactions), so the Expresso DMA Core does not need to flow control requests due to this field. |
| Reserved | 15:9 | roRead-only | 0x0 | |
| rd_pending_ctr | 8:0 | roRead-only | 0x0 | Number of read transactions outstanding for this translation. There cannot be more translations outstanding than the number of simultaneously outstanding transactions supported by the Expresso DMA Core (which is always <512 transactions), so the Expresso DMA Core does not need to flow control requests due to this field. |