TRAN_INGRESS_CAPABILITIES (AXIPCIE_INGRESS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TRAN_INGRESS_CAPABILITIES (AXIPCIE_INGRESS) Register Description

Register NameTRAN_INGRESS_CAPABILITIES
Offset Address0x0000000000
Absolute Address 0x00FD0E0800 (AXIPCIE_INGRESS0)
0x00FD0E0820 (AXIPCIE_INGRESS1)
0x00FD0E0840 (AXIPCIE_INGRESS2)
0x00FD0E0860 (AXIPCIE_INGRESS3)
0x00FD0E0880 (AXIPCIE_INGRESS4)
0x00FD0E08A0 (AXIPCIE_INGRESS5)
0x00FD0E08C0 (AXIPCIE_INGRESS6)
0x00FD0E08E0 (AXIPCIE_INGRESS7)
Width32
TyperoRead-only
Reset Value0x1F0C0001
DescriptionIngress AXI Translation - Capabilities

TRAN_INGRESS_CAPABILITIES (AXIPCIE_INGRESS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ingress_size_max31:24roRead-only0x1FMaximum Translation Size.
ingress_size_offset23:16roRead-only0xCMinimum Translation Size.
Reserved15:1roRead-only0x0
ingress_present 0roRead-only0x1Translation Presence Indicator.