TRAN_INGRESS_CONTROL (AXIPCIE_INGRESS) Register Description
| Register Name | TRAN_INGRESS_CONTROL |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address |
0x00FD0E0808 (AXIPCIE_INGRESS0) 0x00FD0E0828 (AXIPCIE_INGRESS1) 0x00FD0E0848 (AXIPCIE_INGRESS2) 0x00FD0E0868 (AXIPCIE_INGRESS3) 0x00FD0E0888 (AXIPCIE_INGRESS4) 0x00FD0E08A8 (AXIPCIE_INGRESS5) 0x00FD0E08C8 (AXIPCIE_INGRESS6) 0x00FD0E08E8 (AXIPCIE_INGRESS7) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Ingress AXI Translation - Control |
TRAN_INGRESS_CONTROL (AXIPCIE_INGRESS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ingress_attr_w | 31:28 | rwNormal read/write | 0x0 | Ingress Write Cache Override. When ingress_attr_enable == 1, the AXI transaction m_awcache port is set to this value when forwarding write transactions hitting this translation to AXI. When ingress_attr_enable == 0, the default cache attributes determined by cfg_pcie_rx_awcache are applied. |
| ingress_attr_r | 27:24 | rwNormal read/write | 0x0 | Ingress Read Cache Override. When ingress_attr_enable == 1, the AXI transaction m_arcache port is set to this value when forwarding read transactions hitting this translation to AXI. When ingress_attr_enable == 0, the default cache attributes determined by cfg_pcie_rx_arcache are applied. |
| ingress_attr_enable | 23 | rwNormal read/write | 0x0 | Ingress Write/Read Cache Override Enable. |
| Reserved | 22:21 | roRead-only | 0x0 | |
| ingress_size | 20:16 | rwNormal read/write | 0x0 | Translation Size. The translation window size in bytes is configured to be 2^(ingress_size_offset+ingress_size). ingress_size must be <= ingress_size_max. |
| Reserved | 15:14 | roRead-only | 0x0 | |
| Reserved | 13:8 | roRead-only | 0x0 | |
| Reserved | 7:5 | roRead-only | 0x0 | |
| Reserved | 4 | roRead-only | 0x0 | |
| ingress_invalid | 3 | rwNormal read/write | 0x0 | Translation Invalidate Enable. |
| ingress_security_enable | 2 | rwNormal read/write | 0x0 | Translation Security Enable. |
| Reserved | 1 | roRead-only | 0x0 | |
| ingress_enable | 0 | rwNormal read/write | 0x0 | Translation Enable. The translation is hit when both of the following are true: * ingress_enable == 1 * ingress_src_base[63:(12+ingress_size)] == AXI Address[63:(12+ingress_size)] |