TRAN_INGRESS_STATUS (AXIPCIE_INGRESS) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TRAN_INGRESS_STATUS (AXIPCIE_INGRESS) Register Description

Register NameTRAN_INGRESS_STATUS
Offset Address0x0000000004
Absolute Address 0x00FD0E0804 (AXIPCIE_INGRESS0)
0x00FD0E0824 (AXIPCIE_INGRESS1)
0x00FD0E0844 (AXIPCIE_INGRESS2)
0x00FD0E0864 (AXIPCIE_INGRESS3)
0x00FD0E0884 (AXIPCIE_INGRESS4)
0x00FD0E08A4 (AXIPCIE_INGRESS5)
0x00FD0E08C4 (AXIPCIE_INGRESS6)
0x00FD0E08E4 (AXIPCIE_INGRESS7)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionIngress AXI Translation - Status

TRAN_INGRESS_STATUS (AXIPCIE_INGRESS) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0
wr_pending_ctr24:16roRead-only0x0Number of write transactions outstanding for this translation.
Reserved15:9roRead-only0x0
rd_pending_ctr 8:0roRead-only0x0Number of read transactions outstanding for this translation.