TSCTLR (A53_ETM_0) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TSCTLR (A53_ETM_0) Register Description

Register NameTSCTLR
Offset Address0x0000000030
Absolute Address 0x00FEC40030 (CORESIGHT_A53_ETM_0)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionGlobal Timestamp Control Register

TSCTLR (A53_ETM_0) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
EVENT 7:0rwNormal read/write0x0An event selector. When the selected event is triggered, the trace unit inserts a global timestamp into the trace streams.