TSSCR (R5_ETM_1) Register Description
Register Name | TSSCR |
---|---|
Offset Address | 0x0000000018 |
Absolute Address | 0x00FEBFD018 (CORESIGHT_R5_ETM_1) |
Width | 32 |
Type | rwNormal read/write |
Reset Value | 0x00000000 |
Description | TraceEnable Start/Stop Control Register |
TSSCR (R5_ETM_1) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
Stop_select | 31:16 | rwNormal read/write | 0 | When a bit is set to 1, it selects a single address comparator 16-1 as stop addresses. For example, bit [16] set to 1 selects single address comparator 1 as a stop address. |
Start_select | 15:0 | rwNormal read/write | 0 | When a bit is set to 1, it selects a single address comparator 16-1 as start addresses. For example, bit [0] set to 1 selects single address comparator 1 as a start address. |