TX_PCIE_MSG_CONTROL (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TX_PCIE_MSG_CONTROL (AXIPCIE_MAIN) Register Description

Register NameTX_PCIE_MSG_CONTROL
Offset Address0x0000000624
Absolute Address 0x00FD0E0624 (AXIPCIE_MAIN)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionPCIe Message Request Execution - Control

TX_PCIE_MSG_CONTROL (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25roRead-only0x0
msg_has_data24rwNormal read/write0x0Message Payload Presence. When msg_has_data == 1, msg_data is the data payload transmitted with the message. msg_has_data must be consistent with msg_code.
msg_tag23:16rwNormal read/write0x0Message Tag[7:0]. Byte 6 of the Message TLP Header. Set to 0x0 if the Tag field is unused by the message.
msg_code15:8rwNormal read/write0x0Message Code[7:0]. Byte 7 of Message TLP Header. Defines the type of Message. Message Codes are defined by the PCI Express Specification and associated ECNs.
msg_fmt_type 7:0rwNormal read/write0x0Message Format and Type. Byte 0 of Message TLP Header. Must be consistent with Message Code.