TX_PCIE_MSG_SPECIFIC_LO (AXIPCIE_MAIN) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

TX_PCIE_MSG_SPECIFIC_LO (AXIPCIE_MAIN) Register Description

Register NameTX_PCIE_MSG_SPECIFIC_LO
Offset Address0x0000000628
Absolute Address 0x00FD0E0628 (AXIPCIE_MAIN)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionPCIe Message Request Execution - Message Specific[31:0].

TX_PCIE_MSG_SPECIFIC_LO (AXIPCIE_MAIN) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
msg_tlp_hdr1131:24rwNormal read/write0x0Byte 11 of Message TLP Header.
msg_tlp_hdr1023:16rwNormal read/write0x0Byte 10 of Message TLP Header.
msg_tlp_hdr915:8rwNormal read/write0x0Byte
9 of Message TLP Header.
msg_tlp_hdr8 7:0rwNormal read/write0x0Byte
8 of Message TLP Header.