Target_Latency_Register_S4 (CCI400) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Target_Latency_Register_S4 (CCI400) Register Description

Register NameTarget_Latency_Register_S4
Offset Address0x0000005130
Absolute Address 0x00FD6E5130 (CCI_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionTarget_Latency_Register_S4

Target_Latency_Register_S4 (CCI400) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
AR_Lat27:16rwNormal read/write0x0AR channel target latency S4
AW_Lat11:0rwNormal read/write0x0AW channel target latency S4