Trigger_counter_value (TPIU) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

Trigger_counter_value (TPIU) Register Description

Register NameTrigger_counter_value
Offset Address0x0000000104
Absolute Address 0x00FE980104 (CORESIGHT_SOC_TPIU)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionThe Trigger Counter Register enables delaying the indication of triggers to any external connected trace capture or storage devices. This counter is only eight bits wide and is intended to only be used with the counter multipliers in the Trigger Multiplier Register, 0x108. When a trigger is started, this value, in combination with the multiplier, is the number of words before the trigger is indicated. When the trigger counter reaches zero, the value written here is reloaded. Writing to this register causes the trigger counter value to reset but not reset any values on the multiplier. Reading this register returns the preset value not the current count.

Trigger_counter_value (TPIU) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TrigCount 7:0rwNormal read/write0x08-bit counter value for the number of words to be output from the formatter before a trigger is inserted.At reset the value is zero and this value has the effect of disabling the register, that is, there is no delay.