UART1_REF_CTRL (CRL_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

UART1_REF_CTRL (CRL_APB) Register Description

Register NameUART1_REF_CTRL
Offset Address0x0000000078
Absolute Address 0x00FF5E0078 (CRL_APB)
Width32
TyperwNormal read/write
Reset Value0x01001800
DescriptionUART 1 Clock Generator Config

UART1_REF_CTRL (CRL_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:25rwNormal read/write0x0reserved
CLKACT24rwNormal read/write0x1Clock active control.
0: disable.
1: enable.
Reserved23:22rwNormal read/write0x0reserved
DIVISOR121:16rwNormal read/write0x06-bit divider.
Reserved15:14rwNormal read/write0x0reserved
DIVISOR013:8rwNormal read/write0x186-bit divider.
Reserved 7:3rwNormal read/write0x0reserved
SRCSEL 2:0rwNormal read/write0x0Clock generator input source.
000: IOPLL
010: RPLL
011: DPLL_CLK_TO_LPD