VDCR1 (R5_ETM_1) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

VDCR1 (R5_ETM_1) Register Description

Register NameVDCR1
Offset Address0x0000000034
Absolute Address 0x00FEBFD034 (CORESIGHT_R5_ETM_1)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionViewData Control 1 Register

VDCR1 (R5_ETM_1) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Exclude_select31:16rwNormal read/write0When a bit is set to 1, it selects single address comparator 16 to 1 for exclude control. For
example, bit [16] set to 1 selects single address comparator 1.
Include_select15:0rwNormal read/write0When a bit is set to 1, it selects single address comparator 16 to 1 for include control. For example, bit [0] set to 1 selects single address comparator 1.