VISSCTLR (A53_ETM_2) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

VISSCTLR (A53_ETM_2) Register Description

Register NameVISSCTLR
Offset Address0x0000000088
Absolute Address 0x00FEE40088 (CORESIGHT_A53_ETM_2)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionViewInst Start-Stop Control Register

VISSCTLR (A53_ETM_2) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
STOP31:16rwNormal read/write0x0Selects which single address comparators are in use with ViewInst start-stop control, for the purpose of stopping trace. Each bit represents a single address comparator, so bit[m] controls the selection of single address comparator m-16.
START15:0rwNormal read/write0x0Selects which single address comparators are in use with ViewInst start-stop control, for the purpose of starting trace. Each bit represents a single address comparator, so bit[n] controls the selection of single address comparator n.