VPLL_TO_LPD_CTRL (CRF_APB) Register Description
Register Name | VPLL_TO_LPD_CTRL |
---|---|
Offset Address | 0x0000000050 |
Absolute Address | 0x00FD1A0050 (CRF_APB) |
Width | 16 |
Type | rwNormal read/write |
Reset Value | 0x00000400 |
Description | VPLL to LPD Clock Divisor. |
Program divisor for VPLL clock source (in FPD) driven to LPD clock generators. Refer to data sheet for frequency limits.
VPLL_TO_LPD_CTRL (CRF_APB) Register Bit-Field Summary
Field Name | Bits | Type | Reset Value | Description |
---|---|---|---|---|
DIVISOR0 | 13:8 | rwNormal read/write | 0x4 | 6-bit divider. |