VPLL_TO_LPD_CTRL (CRF_APB) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

VPLL_TO_LPD_CTRL (CRF_APB) Register Description

Register NameVPLL_TO_LPD_CTRL
Offset Address0x0000000050
Absolute Address 0x00FD1A0050 (CRF_APB)
Width16
TyperwNormal read/write
Reset Value0x00000400
DescriptionVPLL to LPD Clock Divisor.

Program divisor for VPLL clock source (in FPD) driven to LPD clock generators. Refer to data sheet for frequency limits.

VPLL_TO_LPD_CTRL (CRF_APB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
DIVISOR013:8rwNormal read/write0x46-bit divider.