VTCR0 (DDR_PHY) Register Description
| Register Name | VTCR0 |
|---|---|
| Offset Address | 0x0000000528 |
| Absolute Address | 0x00FD080528 (DDR_PHY) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x70032019 |
| Description | VREF Training Control Register 0 |
VTCR0 (DDR_PHY) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| tVREF | 31:29 | rwNormal read/write | 0x3 | Number of ctl_clk required to meet vref step timing (short, middle, long) requirements. Valid values are: 3b000 = No of ctl_clk = 32 3b001 = No of ctl_clk = 64 3b010 = No of ctl_clk = 96 3b011 = No of ctl_clk = 128 3b100 = No of ctl_clk = 160 3b101 = No of ctl_clk = 192 3b110 = No of ctl_clk = 224 3b111 = No of ctl_clk = 256 |
| DVEN | 28 | rwNormal read/write | 0x1 | DRAM DQ VREF training Enable: When set, DQ VREF training will be performed for all enabled byte lanes and all enabled ranks. |
| PDAEN | 27 | rwNormal read/write | 0x0 | Per Device Addressability Enable: When Enabled, each device will receive VREF DQ values independently. Note: This is applicable in DDR4 mode only |
| Reserved | 26 | roRead-only | 0x0 | Returns zeros when read. |
| VWCR | 25:22 | rwNormal read/write | 0x0 | VREF Word Count: The number of times same memory location range is written/read for each loop in VREF training. |
| DVSS | 21:18 | rwNormal read/write | 0x0 | DRAM DQ VREF step size used during DRAM VREF training. The register value of N indicates step size of (N+1). The valid step sizes are 1 to 16. |
| DVMAX | 17:12 | rwNormal read/write | 0x32 | Maximum VREF limit value used during DRAM VREF training. |
| DVMIN | 11:6 | rwNormal read/write | 0x0 | Minimum VREF limit value used during DRAM VREF training. |
| DVINIT | 5:0 | rwNormal read/write | 0x19 | Initial DRAM DQ VREF value used during DRAM VREF training. |