V_BLEND_CHROMA_KEY_ENABLE (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

V_BLEND_CHROMA_KEY_ENABLE (DISPLAY_PORT) Register Description

Register NameV_BLEND_CHROMA_KEY_ENABLE
Offset Address0x000000A1D0
Absolute Address 0x00FD4AA1D0 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionV_BLEND_CHROMA_KEY_ENABLE

V_BLEND_CHROMA_KEY_ENABLE (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:2razRead as zero0x0
M_SEL 1rwNormal read/write0x0If '1' video stream 0 is the master, if
= 0, video stream 1 will be the master, Valid only if bit 0 = 1
EN 0rwNormal read/write0x01 to
Enable chroma keying