V_BLEND_CR_OUTCSC_OFFSET (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

V_BLEND_CR_OUTCSC_OFFSET (DISPLAY_PORT) Register Description

Register NameV_BLEND_CR_OUTCSC_OFFSET
Offset Address0x000000A078
Absolute Address 0x00FD4AA078 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionV_BLEND_CR_OUTCSC_OFFSET:
Offset values for CR before and after matrix multiplication for output color space conversion

V_BLEND_CR_OUTCSC_OFFSET (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:30razRead as zero0x0
POST_OFFSET28:16rwNormal read/write0x0Signed representation of post matrix offset for color component 1
Reserved15:14razRead as zero0x0
PRE_OFFSET12:0rwNormal read/write0x0Signed representation of offset for color component 1