V_BLEND_IN1CSC_COEFF0 (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

V_BLEND_IN1CSC_COEFF0 (DISPLAY_PORT) Register Description

Register NameV_BLEND_IN1CSC_COEFF0
Offset Address0x000000A044
Absolute Address 0x00FD4AA044 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00001000
DescriptionV_BLEND_IN1CSC_COEFF0:Coefficient values from Matrix for input color space convertor(video). A total of 9 values are needed to form 3x3 matrix. The value is scaled by 2^12 and stored in 15-bit signed format.(1bit reserved). 12Bits out of the 15 represent fractional value and 2 bits for decimal value and one signed bit.
The order of programming values is from v0 - v8

V_BLEND_IN1CSC_COEFF0 (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:15razRead as zero0x0
Y2R_C014:0rwNormal read/write0x1000Signed representation of value.