V_BLEND_LAYER0_CONTROL (DISPLAY_PORT) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

V_BLEND_LAYER0_CONTROL (DISPLAY_PORT) Register Description

Register NameV_BLEND_LAYER0_CONTROL
Offset Address0x000000A018
Absolute Address 0x00FD4AA018 (DISPLAY_PORT)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionV_BLEND_LAYER0_CONTROL:
Layer 0 is always video pixel

V_BLEND_LAYER0_CONTROL (DISPLAY_PORT) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:9razRead as zero0x0
BYPASS 8rwNormal read/write0x0Layer 0 passed thro as the blender out
Reserved 7:2razRead as zero0x0
RGB_MODE 1rwNormal read/write0x0Set to 1 when layer 0 it to the Blender is RGB.
EN_US 0rwNormal read/write0x0Set this bit to 1 to enable up sampler